Job Description

Position: CLP/UPF (SI50FT RM 3659)

& Skill Requirement.

Strong understanding of low-power design concepts- power domains, isolations, retention, level shifters, power gating. etc.


Run and debug Conformal Low Power (CLP) checks at various stages (RTL vs UPF, Gate-level vs UPF, etc.).


Identify and resolve power domain connectivity issues, isolation/retention cell errors, and power intent mismatches.


Very well verse with UPF syntax & commands to participate in UPF development/modification process


Identify/resolve the different CLP problems all the stages.


Analysis all the CLP Error & Warnings tag and functional issues and provided the feedback to backend team till sign- off stage


Collaborate with design, synthesis, and physical design teams to resolve low-power verification issues.


Support sign-off verification and ensure design meets low-power intent requirements.


Performed SOC level CLP RTL, SYN and PNR runs and debugged it


Participate in Review of CLP Warning/Errors with Design & IP teams


Experience in Conformal Low power tool & Fusion compiler is must

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Job Category:

Others

Job Type:

Full Time

Job Location:

Bangalore

Experience:

5+ years

Notice period:

0-30 days