Atpg/scan Insertion Dft

Year    KA, IN, India

Job Description

Overview:

WHAT YOU DO AT AMD CHANGES EVERYTHING





At AMD, our mission is to build great products that accelerate next-generation computing experiences - from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges--striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.


Together, we advance your career.



Responsibilities:

SE

NIOR

SILICON DESIGN ENGINEER

As key member of the AMD EPYC Server team, the successful candidate will play a significant role in ensuring the quality of next generation EPYC Server SoCs through structural DFT, Automatic Test Pattern Generation (ATPG) and Logic Built-In Self-Test (LBIST) techniques.

Primary responsibilities will include

Working closely with the Architecture team to understand the DFT Architecture and implementation

Interfacing with the Design teams to ensure DFT design rules and guidelines are met

Working with the PD team to ensure to correct DFT implementation and closing timing

Generating high quality manufacturing test patterns for stuck-at, transition fault models and through the use of on-chip test compression techniques.

Simulating and verifying the ATPG and LBIST patterns

Analyzing and working with the different stakeholders to get the required design changes in to get the maximum ATPG coverage

Working with the Product engineering teams on the delivery of manufacturing test patterns.

Working with the Product Engineering teams on Silicon bring-up and debugs

Developing, enhancing and maintaining scripts as necessary


Requirements:

Exposure to DFT Architecture and Design

Good working knowledge of ATPG tools (Mentor TK)

Exposure to Static timing analysis & Timing closure is required.

Excellent hands-on debug skills and scripting skills are critical.

Must have good communication skills and the ability to work in a worldwide team environment.


Qualifications:

B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering with 5+ years of DFT experience


Qualifications:

Benefits offered are described:

AMD benefits at a glance

.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

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Job Detail

  • Job Id
    JD4431982
  • Industry
    Not mentioned
  • Total Positions
    1
  • Job Type:
    Full Time
  • Salary:
    Not mentioned
  • Employment Status
    Permanent
  • Job Location
    KA, IN, India
  • Education
    Not mentioned
  • Experience
    Year