Job Description

Job Title -DesignWare IP Verification Team Lead

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished verification engineer with a passion for excellence and a proven record of delivering robust, high-quality IP solutions. You thrive in a fast-paced, dynamic environment and are motivated by the opportunity to work on next-generation connectivity protocols that serve commercial, enterprise, and automotive markets. With a solid educational foundation in Electrical/Electronics Engineering (BSEE with 6+ years or MSEE with 5+ years of relevant experience), you possess deep expertise in System Verilog and state-of-the-art verification methodologies such as UVM, OVM, and VMM. Your hands-on experience in building HVL-based test environments and extracting meaningful verification metrics sets you apart as a technical leader in your field.


You are highly collaborative, valuing knowledge sharing and contributing to a culture of continuous improvement. Your familiarity with protocols like MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, and USB enables you to quickly adapt to new projects and deliver impactful results. Your analytical mindset, exceptional debugging abilities, and drive to exceed quality metrics ensure the delivery of world-class solutions. Proficient in scripting languages such as Perl, TCL, and Python, you efficiently automate processes to enhance team productivity. Strong communication skills, a global perspective, and a proactive attitude enable you to work seamlessly with cross-functional and multi-site teams. Above all, you are a lifelong learner, embracing challenges, adapting to new technologies, and committed to shaping the future of silicon design.

What You'll Be Doing:

Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and the latest verification methodologies. Develop and execute comprehensive test plans, ensuring both unit-level and system-level requirements are thoroughly validated. Design, code, and debug sophisticated testbenches, test cases, and functional coverage models to validate complex IP functionalities. Perform detailed functional coverage analysis and manage regression testing to achieve and maintain high-quality metrics. Collaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure. Leverage scripting languages (Perl, TCL, Python) to automate verification flows, streamline processes, and boost team productivity. Contribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.

The Impact You Will Have:

Deliver high-quality, robust IP cores that power mission-critical applications in commercial, enterprise, and automotive domains. Drive innovation in verification methodologies, setting industry standards for efficiency and comprehensive coverage. Accelerate time-to-market by identifying and resolving design and verification issues early in the development lifecycle. Enhance Synopsys' reputation as an industry leader in silicon IP and verification through technical excellence and a customer-focused approach. Mentor and support junior engineers, fostering a culture of learning, collaboration, and continuous improvement. Contribute to the success of global, multi-site R&D teams by providing technical expertise and driving effective cross-functional collaboration.

What You'll Need:

BSEE with 6+ years or MSEE with 5+ years of relevant experience in ASIC or IP verification. Expertise in developing System Verilog-based verification environments and testbenches. Extensive hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools. Proficiency in UVM, OVM, or VMM verification methodologies; exposure to formal verification is highly desirable. Solid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB. Familiarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus. Demonstrated ability to work with functional coverage-driven methodologies and deliver on quality metric goals.

Who You Are:

Analytical thinker with exceptional problem-solving and debugging skills. Excellent verbal and written communication abilities. Team player who thrives in collaborative, multi-site environments. Proactive, self-motivated, and able to take initiative on challenging projects. Detail-oriented, quality-focused, and driven by a desire to excel. Adaptable and eager to continuously learn and apply new technologies.

The Team You'll Be A Part Of:

You will join the Solutions Group's DesignWare IP Verification R&D team, a highly skilled and diverse group of engineers dedicated to delivering world-class IP cores for next-generation connectivity. The team operates in a collaborative, multi-site environment, leveraging global expertise to solve complex verification challenges. Together, you will drive innovation, share knowledge, and uphold Synopsys' reputation for technical leadership and excellence.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.