Asic Rtl Design Engineer
Job Description
Making Changes to the RTL in Verilog / System Verilog as per the Design Specifications Compile and Elaborate the RTL in Simulator Running the Lint / CDC / Low Power Design Checks Releasing the RTL to the SoC as per the Qualcomm Release process Supporting the SoC Integration of the Core Minimum Qualifications: Bachelor Of Engg in Electronics or equivalent discipline with 3yrs Experience Min. Preferred Qualifications: Experience in designing boolean logic circuits. Experienced in coding with Verilog / System Verilog. Experience in Tool flow for RTL Compilation / Lint Checks / Clock Domain Crossing Checks. Knowledge of STA / LEC is preferred. Bachelors/Masters Degree.
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Job Detail
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Job IdJD3171885
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IndustryNot mentioned
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Total Positions1
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Job Type:Full Time
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Salary:Not mentioned
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Employment StatusPermanent
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Job LocationHyderabad, Telangana - Secunderabad, Telangana, India
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EducationNot mentioned
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ExperienceYear