Job Description

Position: ASIC Design Engineer Experience: 8 15 Years
Location: Hyderabad :
Contribute to the design, implementation, and integration of SoCs.
Perform micro-architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks.
Support prototyping, test program development, chip validation, and lifecycle management through production maturity.
Collaborate closely with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams across all stages of ASIC development. Qualifications & Skills:
8+ years of experience in RTL logic design, verification, synthesis, and timing optimization.
Strong ability to write clear and implementable micro-architecture specifications.
Expertise in Verilog RTL coding and SoC integration.
Solid understanding of assertions, coverage analysis, RTL synthesis, and timing closure.
Hands-on experience with interface protocols like PCIe, USB, Ethernet, DDR/LPDDR4/5, I2C/I3C, eSPI, SPI, etc.
Experience in design bring-up and debug on FPGA-based emulation platforms such as HAPS or Veloce.
Proficiency in scripting languages (Perl, Python).
Must have completed at least one full tape-out cycle.
Preferred:
Silicon bring-up and debug experience.
Familiarity with repository and bug tracking tools like Bitbucket, Jenkins, and JIRA.

Skills Required