Job Description

Project Role :

Analog Layout Engineer

Project Role Description :

Design the physical layout of analog circuits, ensuring proper component placement and routing for optimal performance. Address parasitic effects, signal integrity, and power distribution to meet design specifications. Collaborate to ensure the layout meets functional, electrical, and manufacturing requirements.

Must have skills :

Analog Layout

Good to have skills :

NA

Minimum

3

year(s) of experience is required

Educational Qualification :

15 years full time education



Summary: As an Analog Layout Engineer, you will engage in the intricate process of designing the physical layout of analog circuits. A typical day involves ensuring optimal component placement and routing to enhance performance. You will address critical aspects such as parasitic effects, signal integrity, and power distribution, all while collaborating with team members to ensure that the layout adheres to functional, electrical, and manufacturing specifications. Your role is pivotal in translating design concepts into tangible layouts that meet stringent requirements, contributing to the overall success of the project. Roles & Responsibilities: - Expected to perform independently and become an SME. - Required active participation/contribution in team discussions. - Contribute in providing solutions to work related problems. - Conduct thorough reviews of layout designs to ensure compliance with specifications and standards. - Collaborate with cross-functional teams to address any layout-related challenges and implement effective solutions. Professional & Technical Skills: - Must To Have Skills: Proficiency in Analog Layout. Working on layout design of owned blocks with Cadence Virtuoso XL. Working on block and top-level level layout verification with Calibre. Extensive PAD Ring and Top/Chip level layout experience Working with analog/mixed-signal and digital design teams to ensure proper layout design o Block level floor planning and layout o IC top level floor planning and area estimation o Using recommended layout and verification techniques, tools, and flows to produce optimal designs o Generate post-layout extraction o Create layout related documentation and conduct layout reviews Preferably experience in TSMC, Finfet, SERDES/ADC/DAC/PLL - good to have but not mandatory. - Strong understanding of layout design tools and methodologies. - Experience with parasitic extraction and signal integrity analysis. - Familiarity with design for manufacturability principles. - Ability to work collaboratively in a team-oriented environment. Additional Information: - The candidate should have minimum 3 years of experience in Analog Layout. - This position is based at our Bengaluru office. - A 15 years full time education is required.




15 years full time education