We are seeking an experienced Analog Front-End Design Automation Engineer to develop, automate, and support analog design flows and EDA infrastructure. You will collaborate with analog and layout teams to enhance productivity, build reusable automation frameworks, and ensure reliable design sign-off processes.
Key Responsibilities
Develop and support analog design automation flows for schematic entry, simulation setup, and multi-corner verification.
Automate schematic generation, simulation scripting, Monte Carlo/statistical analysis workflows.
Integrate with Cadence Virtuoso, Spectre, ADE-XL, ADE Assembler, and ADE Explorer.
Build signoff-quality parasitic extraction flows using Synopsys StarRC.
Automate netlist preparation, LVS matching, RC back-annotation, and post-layout simulation flows.
Support layout-versus-schematic (LVS) and post-layout verification.
Create reusable infrastructure for simulation result analysis, constraint checking, and flow regression.
Debug tool and automation issues and coordinate with EDA vendors.
Provide documentation, training, and support to design teams.
Evaluate and recommend new EDA tools and workflow improvements.
Qualifications
Bachelor's or Master's in Electrical Engineering, Computer Science, or related field.
5+ years experience
in EDA infrastructure or analog design automation.
Strong hands-on experience with
Cadence, Synopsys, and Mentor Graphics
tools.
Proficiency in scripting languages (Python, Perl, Shell).
Experience with
license management tools
and methods.
Familiarity with
high-performance computing (HPC)
environments and resource management.
Preferred Skills
Background in analog circuit design environments.
Strong analytical and problem-solving abilities.
Ability to collaborate with cross-functional engineering teams.
Job Types: Full-time, Permanent
Work Location: In person
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