Job Description

SMTS Silicon Design Engineer

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Bangalore, India Engineering 64609

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WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_

Physical Design -RTL Lead Engineer

In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Servers and Personal Computers as well as Graphics Cards and VR sets. The UMC FEINT/Implementation team is responsible for Synthesis, Timing closure/CDC/LINT/ DFx for very high speed (>2G) design.

THE PERSON:

As a Synthesis design engineer, you will work with architects/designers for IP development

KEY RESPONSIBILITIES:

+ Design synthesis: Performing logical and physical synthesis of blocks in IP
+ Design analysis: Analyzing and verifying that the design meets requirements for functionality, performance, and area
+ Design constraints: Defining synthesis design constraints and resolving STA issues
+ Timing analysis: Analyzing timing arc and liberty quality, and providing suggestions for fixing timing violations
+ Design quality checks: Completing all design quality checks and data quality checks (CDC/RDC/LINT/No clock flops etc)
+ Collaboration: Working with RTL engineers to fix timing issues
+ Tool evaluation: Driving new tool evaluation and methodology refinement
+ ECO Implementation :Develop/enhance auto ECO generation scripts for timing closure and ECO implementation
+ Power: Low power optimizations/UPF

PREFERRED EXPERIENCE:

Synthesis engineers should have prior experience with:
+ Synopsys tools for ASIC synthesis and timing constraints
+ Strong background in Timing analysis and CDC
+ Experience in CDC/RDC/LINT closure
+ Familiar with power intent definition, implementation (UPF)
+ Knowledge of various implementation and architectural techniques for low power optimization.
+ Verilog and System Verilog
+ Perl/TCL/Makefile scripting
+ Power Analysis using Power Artist and PTPX
+ LEC, LP signoff tools
+ VLSI front end design steps

ACADEMIC CREDENTIALS:

Master/Batchers Experience:12+Years


#LI-SR5

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.